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Verification

Verification challeges :

Biggest challenge in IC design is verification because the cost of single error is huge. Verification is both time consuming and requires large amount of resources. Types of verification tasks can be classified into two categories :

1. functional verification : check the functionality of synthesised and optimized design against golden representation of design.
2. implementation verification : Once placement and routing is over. The design is checked for functional correctness once again. Timing and power constraints are also verified.

Black box verification methods include Simulation, and Emulation and hardware accelaration.

White box verification methods involve use of formal methods for example Assertion based Verification

 

Assertion Based Verification

Assertion based verification is aimed at Digital Designers. ABV is a white-box verification technique. Unlike Simulation it is not applied on the block level once the design is complete. Assertion based verification can be applied alongside design process. In-fact assertion based verification entities reside in the HDL description of the design.

Assertions are active comments embedded with in the design. Assertions turn design specification into verification objects. Assertions can be used to :

  • monitor signals on interfaces that connect different blocks
  • track expected behaviour of a gate, flip-flop or module
  • watch for fobidden behaviour with-in a design block

Assertions are used to capture funcational specifications and assumptions of the design. An example below captures some possible assertions that can be embedded in the HDL description of the design. Since assertions travel with IP, they can be reused. Some examples of assertions are as follows :

  • Invariants : To check condition like inputs A and B should never be both high.
  • Sequences : If a signal A is high in one cycle then signal B should be high in next clock cycle and C must be high in next cycle.
  • Eventualities : all requests have to be granted eventually. This assertion can be captured by using eventuality.

Advantages of Assertion based design :

  1. Improves quality of design: assertions are "specifications" that are embedded into the design. This captures the designers intent and assumptions more closely. This also helps to define the protocol that should exist at the interface between various modules.
  2. Accelerates Debugging: During its entire life cycle design can be continously checked for assertions. Assertions allows designer to check whether or not design and its environment implement interface correctly. Internal signals can be monitored to ensure that the design operates correctly.
  3. IP integration is faster: IP interface with other sections of design may have problems which are easily identified by assertions. Assertions embedded in IP can identify errors in IP.

Languages Used to define assertions :

  • Implicit assertions are supported by HDLs like Verilog and VHDL. These assertions are added at the time of design analysis, synthesis and HDL analysis.
  • Explicit assertions are user defined assertions. Such assertions are provided by EDA vendors in form of Library like OVL. Academic languages loke CTL, LTL and automata provide a way to define explicit assertions.

Emulation and Hardware Acceleration

Emulator is a hardware device that can be used to emulate a piece of hardware functionality. It is commonly used as a debugging tool to test a system under development for functional correctness..

Emulation is a faster solution to verification problem. In Emulation a portion of emulatable design is synthesised and optimized. The compiled design is then loaded onto an emulator. Rest of the design is simulated by the workstations that are connected to the Emulator. Remember only the portion of the design that is being tested resides on the Emulator. Emulators are able to provide execution speed close to real time. This allows verification engineers to reduce verification time.

Emulation system typically consists of small number of large FPGAs. This provides multi-million ASIC-equivalent gate capacity. Such an emulation system comes as a seperate box. Emulation box can be connected to a collection of workstations using PCI card. The workstations are connected via emulation network architecture.

A complex IC is typically divided into number of different modules. Each module is develeped by a seperate team of designers. Each team verifies the functionality of its own module. The modules then go to an integration team which integrates all the modules and caries out verification. With emulation providing faster methods of design verification last minute changes can be incorporated in the design. This significantly reduces time to market.



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